A Novel Design of Low-Power 1-Bit CMOS Full-Adder Cell using XNOR and MUX
Journal Title: INTERNATIONAL JOURNAL OF MANAGEMENT & INFORMATION TECHNOLOGY - Year 2013, Vol 7, Issue 3
Abstract
This paper process a novel design for low power 1-bit CMOS full adder using XNOR and MUX, with reduced number of transistors using GDI cell. The circuits were simulated with supply voltage scaling from 1.2V to 0.6V &0.6V to 0.3V. To achieve the desired performance of power delay product, area, capacitance the transistors with low threshold voltage were used at critical paths and high threshold voltage at non critical paths. The results show the efficiency of the proposed technique in terms of power consumption, delay and area.
Authors and Affiliations
Dayadi Lakshmaiah, Dr. M. V. Subramanyam, Dr. K. Sathya Prasad
Keywords
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- EP ID EP654341
- DOI 10.24297/ijmit.v7i3.702
- Views 190
- Downloads 0
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