A Reliable implementation of Security-Enabled Architecture with area optimized symmetric Cryptography
Journal Title: International Journal of Research in Computer and Communication Technology - Year 2014, Vol 3, Issue 12
Abstract
My project specifies a symmetric Cryptography technique which provides same keys to Cipher and Decipher to transfer the information for reducing the design complexity and AES (Advanced Encryption Standard) which provokes high security. The transferred information was stored securely in the memory unit. By implementing this design, the results can be accomplished that the optimized area is required to integrate the chip with the gate count of 22618, here shown that gate elements are reduced up to 53.98% in comparison with earlier methods and also providing the similar security as well as reduced power consumption of 43.907mw.
Authors and Affiliations
M. Suresh Kumar, G. S. S. Prasad
Keywords
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