An Innovative Design solution for minimizing Power Dissipation in SRAM Cell
Journal Title: International Journal of engineering Research and Applications - Year 2017, Vol 7, Issue 5
Abstract
Over the years, the development of the logic on the chip is increased. To sustain and drive the logic flow, various techniques and SRAM cell designs have been implemented. The basic element of memory design is 6T SRAM cell. But while dealing with this 6T SRAM cell there are some issues with the parametric analysis on the performance of the cell. This paper presents an innovative design idea of new 8T RAM cell with various parametric analysis. The proposed cell is compared with the standard cell in terms of different parameters such as area, speed and power consumption along with the loading effect with the increase in load capacitance on the cell. The structure is designed with CMOS 45 nm Technology with BSIM 4 MOS modelling using Microwind 3.5 software tool.
Authors and Affiliations
Miss. Varsha Phad, Prof Swati Shetkar
Keywords
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- EP ID EP391102
- DOI 10.9790/9622-0705012528.
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