Analysis Of High Speed Wallace Tree Multiplier Using Compressors For DSP Applications
Journal Title: International Journal of engineering Research and Applications - Year 2018, Vol 8, Issue 7
Abstract
Multiplication is an important arithmetic operation employed in digital systems and signal processing applications. Most of the multipliers are time, area and power consuming circuits. Improvement in any of these parameters will improve the efficiency of the circuit. But ever increasing demand for faster multipliers motivated several researchers to go a step ahead and present some novel approach. This work presents an analysis & approach towards the reduction of delay in the Wallace tree multipliers by using compressors with full adders and half-adders for partial product reduction. The proposed multiplier has been analyzed using Xilinx ISE Design Suite 7.1, Modelsim and Cadence Virtuoso tool.
Authors and Affiliations
Jayalakshmi N, H. Venkatesh Kumar, Kasetty Rambabu
Keywords
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- EP ID EP394981
- DOI 10.9790/9622-0807034448.
- Views 109
- Downloads 0
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