Area Efficient and A High Bit Rate Serial-Serial Multiplier With On-the-Fly Accumulation by Asynchronous Counters
Journal Title: International Journal of Electronics Communication and Computer Technology - Year 2012, Vol 2, Issue 6
Abstract
Traditional Serial-Serial multiplier addresses the high data sampling rate. It is effectively considered as the entire partial product matrix with n data sampling cycle for n×n multiplication function instead of 2n cycles in the conventional multipliers. This multiplication of partial products by considering two series inputs among which one is starting from LSB the other from MSB. Using this feed sequence and accumulation technique it takes only n cycle to complete the partial products. It achieves high bit sampling rate by replacing conventional full adder and highest 5:3 counters. Here asynchronous 1’s counter is presented. This counter takes critical path is limited to only an AND gate and D flip-flops. Accumulation is integral part of serial multiplier design. 1’s counter is used to count the number of ones at the end of the nth iteration in each counter produces. The implemented multipliers consist of a serial-serial data accumulator module and carry save adder that occupies less silicon area than the full carry save adder. In this paper we implemented model address for the 8bit 2’s complement implementing the Baugh-wooley algorithm and unsigned multiplication implementing the architecture for 8×8 Serial-Serial unsigned multiplication.
Authors and Affiliations
Balakrishna Konda| M.Tech Embedded Systems Sri Vasavi Engineering College Tadepalligudem, West Godavari District. Andhra Pradesh, India, Subbarao Madasu| Assistant Professor, Department of ECE Sri Vasavi Engineering College Tadepalligudem, West Godavari District Andhra Pradesh, India
Keywords
Related Articles
- EP ID EP8328
- DOI -
- Views 396
- Downloads 22
Advance Technique in Demodulation of Non-Coherent Binary Phase Shift Keying
Demodulation of Non Coherent Binary Phase Shift Keying, by using STEL -2110A Chip Circuitry VDSP++4.5 software Technique, Both Time and Frequency recovery of the signal is possible, but in this paper only timing recovery...
Reversible Multiplier with Peres Gate and Full Adder
Low Power dissipation and smaller area are one of the important factors while designing multipliers for digital circuits. As multipliers used in digital circuits dissipate large amount of heat whenever there is a tran...
Design and Implementation of 64-Bit Execute Stage for VLIW Processor Architecture on FPGA
FPGA implementation of 64-bit execute unit for VLIW processor, and improve power representation have been done in this paper. VHDL is used to modelled this architecture. VLIW stands for Very Long Instruction Word. This P...
A Novel Low Power Topology in Reversed Nested Miller Compensation Using Triple-Active Capacitance
A novel three-stage amplifier topology for low voltage , low power and large capacitive load applications is proposed . This scheme is called the tripple-active capacitance and resistance in reversed nested Miller compen...
Encryption Visual Projection in Embedded Systems
Embedded systems permeate our everyday lives. From automobiles to elevators, kitchen appliances to televisions, and water heaters to cell phones, we increasingly depend upon embedded systems to operate as expected. A few...