Area-Efficient and High Speed ML MAP Processor Design Using DB/SB Decoding Technique

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Area-Efficient and High Speed ML MAP Processor Design Using DB/SB Decoding Technique

Journal Title: International Journal of Electronics Communication and Computer Technology - Year 2012, Vol 2, Issue 3

Abstract

In communication systems, specifically wireless mobile communication applications, Size and Speed are dominant factors while meeting the performance requirements. Turbo codes play an important role in such practical applications due to their better error-correcting capability. In Turbo decoders, Maximum A Posterior probability (MAP) algorithm has been widely used for its optimum error correcting performance. But it is very difficult to design high-speed MAP Decoder because of its recursive computations. This paper proposes a Max-Log maximum a posteriori (ML-MAP) algorithm with dual mode SB/DB decoding. A Parallel VLSI architecture comprising multiple SISO elements, to form Log Likelihood ratio (LLR) unit in order to reduce the critical path delay. A dual mode single-binary (SB) and double-binary (DB) decoding algorithm has been used to reduce the arbitrary block sizes for high throughput decoding. The computational modules and storages of the dual-mode (SB/DB) MAP decoding are designed to achieve high area utilization. This architecture with a SB/DB decoding can achieve comparable processing speed about 11 % and area efficiency of 5.71 bits/mm2.

Authors and Affiliations

P. Maniraj Kumar| Department of ECE, PSNA College of Engineering & Technology, Dindigul, India Mani1376@yahoo.com, Dr. S. Sutha| Department of EEE, Anna University of Technology, Panruti, India suthapdmanabhan@gmail.com

Keywords

EP ID EP8278
DOI -
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