D Flip Flop with Low Power Clocking System by using MTCMOS and Slumber Keeper Technique
Journal Title: International Journal for Research in Applied Science and Engineering Technology (IJRASET) - Year 2017, Vol 5, Issue 4
Abstract
power utilization plays an significant function in any integrated circuit. We are having three main challenges in semiconductor technology. in any integrated circuit clock sharing networks and storage elements such as flip-flop consume more power. in this paper, an assortment of techniques to implementing flip-flops with low power clocking structure is analyzed. among those different techniques clocked pair communal flip-flop using mtcmos(cpcff-mt) consume smallest amount of power than conditional statistics mapping flip flop (cdsff),conditional expulsion flip flop (ceff) and conservative twin edge triggered flip-flop (teff). we put forward a new (cpcff-mt) with slumbery keeper technique which reduces the power consumption by approximately 30% to 75% than the original cpcff-mt.
Authors and Affiliations
Anusha Kondam
Keywords
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- EP ID EP23813
- DOI http://doi.org/10.22214/ijraset.2017.4106
- Views 293
- Downloads 7
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