Design and Functional Verification of Four Way Set Associative Cache Controller
Journal Title: International Journal of Research in Computer and Communication Technology - Year 2015, Vol 4, Issue 3
Abstract
This project describes the design of a Cache Controller that will handle 32Kbyte 4 ways with 8word block size cache. A cache controller is a device that used to sequence the read and write of the cache storage array. Most of modern microprocessor is designed with multiple core architecture that will lead to massive traffic of cache data transfer. By taking the advantage of using temporal locality and spatial locality to the cache, the problem can be solved. With this solution, a controller capable to handle huge amount of way and block size need to be designed. This design will be implemented using Questasim software. It was developed base on Verilog coding. Using the same software, a test bench was constructed to test the functionality of the controller.
Authors and Affiliations
Pooja Shaileshbhai Bavishi
Keywords
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