Design and Implementation of Carry Tree Adders using Low Power FPGAs
Journal Title: International Journal of Advanced Research in Computer Engineering & Technology(IJARCET) - Year 2012, Vol 1, Issue 7
Abstract
The binary adder is the critical element in most digital circuit designs including digital signal processors (DSP) and microprocessor data path units. As such, extensive research continues to be focused on improving the power delay performance of the adder. To resolve the delay of carry-look ahead adders, the scheme of multilevel-look ahead adders. These adders have tree structures within a carry-computing stage similar to the carry propagate adder. However, the other two stages for these adders are called pre-computation and post-computation stages. In pre-computation stage, each bit computes its carry generate/propagate and a temporary sum. In the post-computation stage, the sum and carry-out are finally produced. The carry-out can be omitted if only a sum needs to be produced
Authors and Affiliations
Sivannarayana G , Raveendra babu Maddasani , Padmasri Ch
Keywords
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