Design and Implementation of High-performance Logic Arithmetic Full Adder Circuit based on FinFET 16nm Technology – Shorted Gate Mode
Journal Title: International Journal of Science and Research (IJSR) - Year 2015, Vol 4, Issue 4
Abstract
Fin-type field-effect transistors (FinFETs) are promising substitutes for bulk CMOS at the nanoscale. FinFETs are double-gate and multi-gate devices. Double-gate (DG) FinFETs has better Short Channels Effects (SCEs) performance compared to the conventional CMOS and stimulates technology scaling. The two gates of a FinFET can either be shorted for higher performance or independently controlled for lower leakage or reduced transistor count. In this paper, we are designing a 16nm Double-gate (DG) FinFETs and extracting their transfer characteristics by using Synopsys HSPICE simulation tool. Full Adder is implemented in CMOS with 32nm technology and FinFET-shorted gate mode with 16nm technology along with its working waveform and performance analysis. HSPICE simulations are carried out for the design and results are analyzed.
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