Design & Implementation of 16-bit Carry Skip Adder using Reversible Computing
Journal Title: International Journal of engineering Research and Applications - Year 2018, Vol 8, Issue 8
Abstract
Nowadays, reversible circuits are receiving immense attention because there is no loss of information bit during processing of data. These reversible circuits are better in terms of quantum cost and power consumption. This paper presents the implementation of 16-bit carry skip adder using parity preserving reversible gates. The fault tolerant full adder require to design this proposed circuit can be realized using parity preserving LCG gate and ZPLG gate. Xilinx 14.4 is used to simulate this design.
Authors and Affiliations
Shweta Thakur, Er. Amandeep Singh Bhandari
Keywords
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- EP ID EP395033
- DOI 10.9790/9622-0808016872.
- Views 147
- Downloads 0
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