Design Of A Rceat Architecture For Detecting Multi- Bit Error In RFID
Journal Title: International Journal of Research in Computer and Communication Technology - Year 2014, Vol 3, Issue 10
Abstract
Radio Frequency Identification (RFID) plays an important role in Warehouse Management, especially during the automatic identification of items. Unfortunately, a warehouse environment has electromagnetic interferences causing read failures in the RFID system. Here, we will considering networking environment, the cyclic redundancy check is widely utilized to determine whether error have been introduced during transmission over physical links. Cyclic redundancy check is extensively used for encoding and decoding communication channel burst errors, where a transient fault causes several adjacent data errors. In this method, the transmitter divides of the message by an agreed-upon polynomial called the generator and concatenates the calculated residue to the message. The receiver divides what it receives by the generator again. A zero residue indicates error-free transmission and a nonzero residue is interpreted as an error. In this paper, the RFID system employs the Cyclic Redundancy Check (CRC) as an error detection scheme. This paper presents a proposed Reliable and Cost Effective Anti-collision technique (RCEAT) or Radio Frequency Identification (RFID) Class 0 UHF tag. The RCEAT architecture consists of two main subsystems PreRCEAT and PostRCEAT. The proposed system is designed using Verilog HDL in FPGA SPARTAN 6 device, which has achieved a good validation. The system is simulated using Modelsim and synthesized using Xilinx Synthesis Technology.
Authors and Affiliations
Indugula Anusha Devi, B Bala Krishna, V N M Brahmanandam
Keywords
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