Design of High speed Vedic MAC Unit using Urdhva Tiryakbhyam sutra & comparison with Conventional Architecture
Journal Title: International Journal for Research in Applied Science and Engineering Technology (IJRASET) - Year 2015, Vol 3, Issue 5
Abstract
A major trend in the semiconductor design industry is to continually produce increasingly faster processors. For high speed Processors the main processing bottlenecks is the multiply and Accumulate unit (MAC). The speed of MAC depends greatly on the multiplier. The speed of multiplier greatly depends on the number of multiplication and adder units. In this paper we have proposed an improved time and area efficient MAC unit which employs Vedic multiplier. The Vedic mathematics going to reduce the number of adder and multiplier as compare to the conventional multipliers. So we propose high-speed, efficient area MAC adopting Vedic multiplication sutra based architecture for 2bit, 4bit, 8 bit, 16 bit, 32 bit and 64bit size and compared with present conventional architectures. The proposed MAC unit is coded in Verilog, synthesized and simulated using Xilinx ISE10.1.
Authors and Affiliations
Arpita A. Koli, S. B. Kulkarni
Keywords
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- EP ID EP20612
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