Design of Low Power Double Edge Triggered Phase Detector for DLL Clock Generators
Journal Title: International Journal for Research in Applied Science and Engineering Technology (IJRASET) - Year 2017, Vol 5, Issue 1
Abstract
A DLL based double edge triggered phase detector (DET-PD) is proposed for a clock generator in low power systems. The phase detector plays a vital role in DLL clock generators. To reduce the power consumption, the phase detector is designed by combining both the edges of the clock pulse. The phase detector is designed by Truly Single Phase Clock (TSPC) delay flip flop (DFF) logic which has a faster locking speed. The operating frequency of the design ranges between 250MHz-800MHZ. The design is implemented in 180nm and 65nm CMOS process technology and the average power consumed is6.26mW and 3.92mW respectively.
Authors and Affiliations
V. Yamuna, Mrs. P. Meenakshi Vidya, Dr. S. Sudha
Keywords
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