Design Of Pulse Triggered Flip-Flop And Analysis Of Average Power
Journal Title: International Journal for Research in Applied Science and Engineering Technology (IJRASET) - Year 2015, Vol 3, Issue 2
Abstract
In this brief, Pulse-triggered FF (P-FF) is a single-latch structure which is more popular than the conventional transmission gate (TG) and master–slave based FFs in high-speed applications. Low power design has become one of the main concerns in Very Large Scale Integration design. Among the various building blocks in digital designs, one of the most complex and power consuming is the flip-flop. As transistors used have small area and low power consumption, they can be used in various applications like digital VLSI clocking system, buffers, registers, counters, microprocessors etc. Proper selection of flipflop is necessary in order to satisfy low power and high performance circuit.The investigation of conventional and proposed pulse Triggered flip-flop using pass transistor logic flip-flop is done with comparisons of average power which claims that proposed design is suitable for low power applications. The circuits are simulated with Metal Oxide Semiconductor Field Effect Transistor using TANNER EDA and CANDENCE GPDK180 nm process technology. The average power consumption of proposed pulse triggered flip-flop using pass transistor logic is 40.94μw and the number of transistors used 17.
Authors and Affiliations
P. Ilakya, G. Paranthaman
Keywords
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