DesignandAnalysisofMultimode Single Precision FloatingPointArithmetic Unit Using Verilog
Journal Title: International Journal of Scientific Research and Management - Year 2017, Vol 5, Issue 5
Abstract
This Paper Presents a Design and Analysis of Multimode Single Precision Floating PointArithmetic Unit Using VERILOG Hardware Description Languageon FPGA.The multimode floatingpoint arithmetic unit have addition, subtraction, multiplication and division operations. The device usedis Zed Board Zynq Evaluation and Developed Kit (xc7z020clg484-1) on which the proposed design willbe physically verified. We design and analyse the efficient multimode floating point arithmetic unit forIEEE 754 floating point number system, which gives a better implementation in terms of area ofhardware. We have four separate units for four different arithmetic operations, by combining additionand subtraction unit into one and multiplication and division unit into one and by efficient optimization.The result of this combination is to reduce the number of LUTs used in FPGA. Thus the total area ofhardware required willbe reduced. The LUTs reduction is 14% and area reduction is 19%.
Authors and Affiliations
Sachin saraswat
Keywords
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