Abstract

Distributed arithmetic (DA) is commonly used for signal processing algorithms where calculating the inner product of two vectors comprises most of the computational workload. An important signal processing area is adaptive filtering. Adaptive filtering is extensively used in several signal processing applications including signal de-noising, and channel equalization for communication and networking systems. But, DA has its issues also. The main problem here is the updating of the memory table. Several methods have been adopted to accelerate memory updating, but it had led to additional memory usage and convergence speed. Hence it is necessary to develop structures for an adaptive DA filter with the maximum reduction of these disadvantages. Various methods can be adopted to achieve this result. One among them is parallel lookup table (LUT) update and concurrent implementation of filtering and weight-update operations. The DA-based inner-product computation can be done by conditional signed carry-save accumulation instead of conventional adder-based shift accumulation and a fast bit clock for carry-save accumulation but a much slower clock for all other operations can also be adopted. The coding of each module is simulated and synthesized using the Xilinx ISE Design Suite 12.1 and ISim Simulator.

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