FPGA Design of Pipelined 32-bit Floating Point Multiplier
Journal Title: International Journal of Computational Engineering and Management IJCEM - Year 2013, Vol 16, Issue 5
Abstract
An architecture for a fast 32-bit floating point multiplier compliant with the single precision IEEE 754-2008 standard has been proposed in this paper. Verilog is used to implement a technology-independent pipelined design. Floating Point Multiplier is synthesized and targeted for Xilinx Spartan-3E FPGA.
Authors and Affiliations
Shaifal, Sakshi
Keywords
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- EP ID EP125724
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