High Performance FPGA Based Optimization Techniques for DSP Blocks
Journal Title: International Journal of engineering Research and Applications - Year 2017, Vol 7, Issue 11
Abstract
A digital circuit Optimization is needed to attain higher performance include terms like minimizing the area occupancy and increasing the speed of operation. In any digital circuit the critical path (longest path delay) decides the operating frequency of the system. The operating frequency of digital circuits can be increased by several techniques such as pipelining and wave-pipelining. The proposed technique is evaluated by implementing 4x4 array multiplier, 4-tap FIR filter using array multiplier and 4-tap DA based FIR filter by using three different schemes: non-pipelining, pipelining and wave-pipelining on Spartan 3E FPGA. The WP array multiplier and FIR filters are operating at higher frequency than by using conventional pipelining and non-pipelining techniques.
Authors and Affiliations
B. Krishna, M. Srinu
Keywords
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- EP ID EP392853
- DOI 10.9790/9622-0711045055.
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