High Speed and Reduced Power – Radix-2 Booth Multiplier
Journal Title: International Journal of Computational Engineering and Management IJCEM - Year 2013, Vol 16, Issue 2
Abstract
A multiplier is one of the key hardware blocks in most digital and high performance systems such as FIR filters, digital signal processors and microprocessors etc. A system’s performance is generally determined by the performance of the multiplier because the multiplier is generally the slowest element in the whole system. Furthermore, it is generally the most area consuming. Hence, optimizing the speed and area of the multiplier is a major design issue. However, area and speed are usually conflicting constraints so that improving speed results mostly in larger areas. So here idea is to find out the best trade off solution among the both of them. The result of this work helps to make a proper choice among different adders in booth multiplier that is used in different digital applications according to requirements.
Authors and Affiliations
Sakshi Rajput, Priya Sharma, Gitanjali, Garima
Keywords
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