High-speed architecture design of integer motion estimation for H.264/AVC
Journal Title: Science Paper Online - Year 2008, Vol 3, Issue 1
Abstract
As the latest video coding standard, H.264 significantly outperforms previous standards. The price is that the computation of motion estimation increase by times. For meeting the requirement of huge computation, this paper proposes a hardware architecture design of integer motion estimation for H.264. The design refines part processing steps of SAD process element (PE) to compose a new PE shared by SAD PE matrixes. The improved architecture is implemented with 134.6×103 logic elements that have decreased by 31%. Through decomposing adders and the boolean calculation steps in SAD PE’s units to calculate absolute values, the design decreases the granularity of PE’s pipelining structure. The SAD process element matrix can work at 166 MHz.
Authors and Affiliations
LIU Rongke LIN Xin
Keywords
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