Implementation of a Capacitor Less Low Dropout Voltage Regulator on Chip (SOC)
Journal Title: The International Journal of Technological Exploration and Learning - Year 2014, Vol 3, Issue 3
Abstract
In this paper we have implemented a linear voltage low drop out regulator for efficient power management considering the fact in mind that voltage regulators provide a constant voltage supply to the circuits. We replace the common drain by common source pass element to improve efficiency and reduce the voltage drop across the device. This research paper includes the process to remove the external capacitor allowing for greater power system (soc) application. A compensation scheme is presented that provides both a fast transient response and full range alternating current (ac) stability from 0 to 50 mA load current even if the output load is as high as 100 pf. A 2.7-v capacitorless LDO voltage regulator with a power supply 3 v was designed with a dropout voltage of 300 mv.
Authors and Affiliations
Shailika Sharma| M.TECH-Advance Electronics and Communication JSS Academy of Technical Education New Delhi, India, Himani Mittal| Department of E&C A.P-J.S.S Academy of Technical Education Noida, India
Keywords
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- EP ID EP8547
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