Abstract

Large scale integration of LSI has resulted in an increase in small delay defects. Small delay variations are induced by process variation, power supply noise as well as resistive opens and shorts. In this paper we use flip-flop design which is used in performing internal path-delay test and measurement using scan path technique. The proposed method measures delay of the explicitly sensitized paths using on chip variable clock generator. This method produces test patterns using Automatic Test Pattern Generator (ATPG).

Authors and Affiliations