IMPLEMENTATION OF USB FOR HIGH SPEED DATA TRANSFER
Journal Title: IJAR-Indian Journal of Applied Research - Year 2019, Vol 9, Issue 3
Abstract
In this paper we design the physical layer of USB3.0 with Super Speed functionality. The physical layer consists of the PCI express and PIPE interface. The design can transfer data serially from transmitter to receiver at 2.5 Gb/s. The design generates a clock that runs at a frequency of 125MHz to transfer data in parallel interfaces. The architecture of the USB3.0 physical layer is proposed in this paper. The architecture is designed and implemented using Verilog HDL in Xilinx Vivado 2017.4
Authors and Affiliations
Kuldeep Sharma
Keywords
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