Improved Stability of 4H Sic-MOS Devices after Phosphorous Passivation with Etching Process
Journal Title: International Journal of Fundamental Physical Sciences - Year 2014, Vol 4, Issue 2
Abstract
Phosphorous passivation of the interface (4H-SiC/SiO2) improves interface trap density (Dit) from 1013 eV-1cm-2 to 2×1012eV-1cm-2 at 0.2eV below the conduction band edge of 4H-SiC. Due to the formation of phosphosilicate glass (PSG) layer during P passivation, metal-oxide-semiconductor capacitors (MOS-Cs) are highly unstable. Under bias-temperature stress (BTS) there is a very large shift in the flat band voltage, VFB, (independent of the bias polarity) of MOS-Cs. In this paper, we proposed a new method to improve the stability of these devices. The PSG layer formed after passivation is etched-off in buffered oxide etch (BOE) and then capped with deposited oxide. Devices fabricated with this process showed Dit of 4x1012eV-1cm-2, and are stable after BTS test performed at 150oC, +1.5MV/cm. This value of Dit is as good as the-state-of-the-art NO/N2O passivated MOS-C. Also, XPS indicated the presence of P at the interface after etching which explains “NO/N2O –like” Dit for etched PSG MOS-Cs.
Authors and Affiliations
Y. K. Sharma, Yi Xu, M. R. Jennings, C Fisher, P. Mawby, L. C. Feldman, J. R. Williams
Keywords
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- EP ID EP599194
- DOI 10.14331/ijfps.2014.330064
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