Leakage Power Reduction Through Hybrid Multi-Threshold CMOS Stack Technique In Power Gating Switch
Journal Title: International Journal of Advanced Research in Computer Engineering & Technology(IJARCET) - Year 2013, Vol 2, Issue 4
Abstract
In this paper Two Hybrid digital circuit design techniques are produced as Hybrid Multi-Threshold CMOS complete stack technique and Hybrid Multi-Threshold CMOS partial stack technique for reducing the leakage power dissipation in mode transistion.Tri-modal switch are performance depends on these two techniques reduce the leakage power dissipation. These technique are implemented in the CADENCE virtuoso tool to find the leakage power dissipation and propagation delay. This proposed Hybrid techniques are proved better leakage power reduction than the MTCMOS techniques.
Authors and Affiliations
R. Divya , J. Muralidharan
Keywords
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