Low power and Area Efficient MDC based FFT for Twin Data Streams
Journal Title: International Journal of engineering Research and Applications - Year 2017, Vol 7, Issue 11
Abstract
Fast Fourier transform (FFT) has become multivariate in many industrial environments. FFT is one of the most employed architecture in multipurpose communication and signal processing systems. The main intent of this paper is to design an efficient Twin Data Streams FFT processor for numerous applications. The FFT architecture used in the Multipath Delay Commutator will process an N / 2 point decimation in time FFT and an N / 2 point decimation in frequency FFT operations of odd and even samples of two Data streams separately to reduce the area and improve throughput. By using the bit reversal operation in the architecture the number of registers will be decreased. Multipath Delay Commutator (MDC) with FFT parallelized architecture is used to achieve high throughput. Modified booth multiplier is used to reduce number of partial products and complexity of the system when compared to serial multiplier.
Authors and Affiliations
M. Hemalatha, R. Ashok Chaitanya Varma
Keywords
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