Low Power Design of A SRAM Cell for Embedded Memory
Journal Title: International Journal of Research in Computer and Communication Technology - Year 2013, Vol 2, Issue 11
Abstract
This paper presents a new SRAM cell to reduce power consumption with the feedback technique by using Schmitt Trigger in the proposed circuitry design. By the proposed design we may reduce the power consumption and area than the existing type of designs. The Schmitt Trigger operation gives better read-stability as well as better write-ability compared to the standard 6T bitcell. This work mainly focuses on the design of a new SRAM cell for reducing the power consumption is implemented in Microwind and DSCH tools. The goal of this project is to develop a circuit level technique that takes advantage of program behavior to reduce power consumption with no performance degradation. With the help of proposed design we may reduce power consumption more than 63.68% and area is overhead. This paper presents a low power consumption SRAM cell and array architecture targeting high performance, low power embedded memory.
Authors and Affiliations
P Kalyana Srinivasa Rao, J Venkata Suman
Keywords
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- EP ID EP27736
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