Multiplier Using Canonical Signed Digit Code
Journal Title: International Journal for Research in Applied Science and Engineering Technology (IJRASET) - Year 2015, Vol 3, Issue 5
Abstract
Real-time implementation of many digital signal processing (DSP) algorithms and multimedia applications are limited by the available speed, energy efficiency, and area requirement of multiplication. This is the major drawback in handheld multimedia devices due to the limited battery lifetimes. A novel canonical signed digit (CSD) iterative multiplier structure in which the conversion from 2's complement to CSD representation is implicitly implemented in real-time.
Authors and Affiliations
Vishwanath B. R. , Theerthesha. T. S
Keywords
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