Design and Implementation of High Speed Carry Select Adder

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 Design and Implementation of High Speed Carry Select Adder

Journal Title: INTERNATIONAL JOURNAL OF ENGINEERING TRENDS AND TECHNOLOGY - Year 2013, Vol 4, Issue 9

Abstract

 Design of area and power-efficient high-speed data path logic systems are one of the most substantial areas of research in VLSI system design. In digital adders, the speed of addition is limited by the time required to propagate a carry through the adder. Carry Select Adder (CSLA) is one of the fastest adders used in many data-processing processors to perform fast arithmetic functions. From the structure of the CSLA, it is clear that there is scope for reducing the area and power consumption in the CSLA. This work uses a simple and efficient gate-level modification to significantly reduce the area and power of the CSLA. The CSLA is used in many computational systems to alleviate the problem of carry propagation delay by independently generating multiple carries and then select a carry to generate the sum. However, the CSLA is not area efficient because it uses multiple pairs of Ripple Carry Adders (RCA) to generate partial sum and carry by considering carry input Cin = 0 and Cin = 1, then the final sum and carry are selected by the multiplexers (mux). This is modified by replacing the RCA with Cin=1 with BEC in the regular CSLA to achieve low area and power consumption. But there is a slight increase in the delay. The delay can be reduced by improving the CSLA by replacing a D-Latch in place of RCA with Cin = 1.in the regular CSLA to achieve high speed addition. The performance of this CSLA is evaluated by implementing an FIR Filter by using the CSLA in the adder part. This work focuses on the performance of CSLA in terms of delay and power and it is found that CSLA is a high speed and low power adder.

Authors and Affiliations

P. Prashanti

Keywords

CSLA D-Latch low power

EP ID EP98963
DOI -
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