Fine Grain Dynamically Reconfigurable Architecture for CMOS Sram

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 Fine Grain Dynamically Reconfigurable Architecture for CMOS Sram

Journal Title: International Journal of Engineering Sciences & Research Technology - Year 30, Vol 3, Issue 4

Abstract

 Cell stability and area are among the major concerns in SRAM cell designs. This paper compares the performance of three SRAM cell topologies which include the conventional 6T-cell,8T-cell and 10T-cell. The cmos devices to achieve the better performance in terms of speed, power dissipation, size and reliability.SRAM(static random access memory)is memory used to store data. The comparison of different SRAM cell on the basis of different parameters is done.6T,8T and 10T SRAM cell are compared on basis of followings:1)Read delay, 2)Write delay, 3)power indulgence. The various SRAM solutions are analyzed in light of an impact on the required area overhead for each design solution given by Area(mm), Power(Mw) and delay(us). Different count of SRAM bitcells(6T, 8T, 10T) are analyzed. Among these 10T SRAM cell is better to immune SI (signal integrity), better STABILITY (Read + Write), Low Power consume bitcell. Inner architecture of FPGA OR CPLD comprised of No of CLB’s interconnecting with inter-logics. (inter-logics like RAM contains SRAM bitcells are used connect the two CLB’s inout)and One CLB contains no of slices . if one CLB comprised of 4 slice , it will communicate with one another using RAM like SRAM cells only

Authors and Affiliations

Dr. A. Senthil Kumar

Keywords

Field programmable gate

EP ID EP117183
DOI -
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