FPGA IMPLEMENTATION AND DESIGN OF LOW POWER SEQUENTIAL FILTER
Journal Title: International Journal of Engineering Sciences & Research Technology - Year 2015, Vol 4, Issue 4
Abstract
We will presents the design and FPGA implementation of sequential digital 8-tap FIR filter using a novel micro programmed controller based design approach. In the paper, the FIR filter is designed for operation controls by micro programmed controller. The proposed FIR filter will be coded in VHDL using modular design approach, and implement in Spartan-3E FPGA. The performance evaluation and synthesis results obtained through Xilinx ISE synthesis tool and functionally checked in Model sim module
Authors and Affiliations
Shivam Singh Sikarwa , Deepak Sharma , Vijay Kumar Sharma
Keywords
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