Implementation of AHB Bus Tracer with Compression and Multi Resolution for SOC
Journal Title: International Journal of Engineering Sciences & Research Technology - Year 30, Vol 3, Issue 3
Abstract
In the system-on-chip (SOC) debugging and performance analysis/optimization, monitoring the on-chip bus signals are necessary. But, such signals are difficult to observe since they are deeply embedded in a SOC and no sufficient I/O pins to access those signals. Therefore, we embed a bus tracer in SOC to capture the bus signals and store them. The stored trace memory can be loaded to the trace analyzer software for analysis. In this paper, we propose an embedded multi-resolution AMBA trace analyzer that provides the trade-off between the trace granularity and the trace depth. It consists of two major trace approaches: (1) the signal monitor/tracing which provides the levels of. Abstraction, and (2) the trace reduction. In the first approach, it allows designers to zoomin/out to preferred level of abstraction to serve different debugging purposes In the second approach, the trace analyzer compresses the traced data according to signal characteristics and the cost of on-chip storage is reduced. The trace data will be decompressed on the host for further observation and debugging. The experimental results show that the proposed approach can reach a good compression ratio of 96% and the trace depth is more than two thousand cycles at the higher abstraction level. The SOC can be verified in field-programmable gate array. In the second approach, the trace analyzer compresses the traced data according to signal characteristics and the cost of onchip storage is reduced. The trace data will be decompressed on the host for further observation and debugging. The experimental results show that the proposed approach can reach a good compression ratio of 96% and the trace depth is more than two thousand cycles at the higher abstraction level.
Authors and Affiliations
D. Parvathi
Keywords
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- EP ID EP106296
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