Optimize Parity Encoding for Power Reduction in Content Addressable Memory
Journal Title: International Journal of Engineering Sciences & Research Technology - Year 30, Vol 3, Issue 11
Abstract
Most memory devices store and retrieve data by addressing specific memory locations. As a result, this path often becomes the limiting factor for systems that rely on fast memory accesses. The time required to find an item stored in memory can be reduced considerably if the item can be identified for access by its content rather than by its address. A memory that is accessed in this way is called content-addressable memory (CAM). However, due to parallel process characteristic, power consumption is always an important Concern when designing CAM circuitry. (i.e) Content addressable memories simultaneously compare an input word to all the contents of memory and return the address of matching locations. The main challenge in CAM design is to reduce power while maintaining speed and low area. Content addressable memory (CAM) or associative memory, is a storage device, which can be addressed by its own contents. This paper presents the CAM low power techniques at architecture level.
Authors and Affiliations
Nisha Sharma
Keywords
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