Review on Reducing the Power in Network-on-chip
Journal Title: International Journal of Engineering Sciences & Research Technology - Year 30, Vol 3, Issue 11
Abstract
Network-on-chip(NoC) is an emerging revolutionary method to integrate numerous cores in a single System-onChip (SoC). The network-on-chip (NoC) design paradigm is recognized as the most viable way to tackle with scalability and variability issues that characterize the ultradeep submicronmeter era. A significant fraction of the overall power dissipation of a network-on-chip (NoC) based system-on-chip (SoC) is due to the interconnection system. The advancements in the future technology makes it possible to place larger number of transistors on a single die, together with many different layers of interconnect and their contribution is expected to increase and compete with the power dissipated by the other elements of the communication subsystem, namely, the routers and the network interfaces (NIs). In this paper, we surveyed recent data encoding techniques aimed at reducing the power dissipated by the network links.
Authors and Affiliations
Akshaya. K. R*
Keywords
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