PATTERN AND POSITION DEPENDENT GATE LEAKAGE AND REDUCTION TECHNIQUE
Journal Title: ICTACT Journal on Microelectronics - Year 2015, Vol 1, Issue 3
Abstract
The leakage power has become a vital downside in modern VLSI technology, with the advent in the area of high performance chips and portable electronics. Thus it is necessarily to invest more time and effort in designing low power chip without sacrificing its high performance. This paper describes a steady state gate leakage based on position and biasing states. As a basic reference universal gates are selected and compared the gate leakage of conventional NAND and NOR gate using 180nm TSMC technology. It is shown that the overall leakage in a NAND -gate is smaller than in a NOR gate if equal size transistors are used. It also compares the leakage value of proposed leakage reduction techniques with conventional NAND gate. Simulation results shows up to 88% in average gate leakage reduction with modified techniques
Authors and Affiliations
Sreekala K S, Krishna Kumar S
Keywords
Related Articles
- EP ID EP198075
- DOI 10.21917/ijme.2015.0022
- Views 146
- Downloads 0
DFAL BASED FLEXIBLE MULTI-MODULO PRESCALER
The quest to have longer battery life and reduced packaging cost has been motivating factor behind developing low power circuits for different applications. Research in adiabatic logic has recently gained momentum and di...
DESIGN AND IMPLEMENTATION OF LOW-NOISE AMPLIFIER FOR ULTRA-WIDEBAND RECEIVER IN 180nm CMOS TECHNOLOGY
This paper presents an ultra-wideband (UWB) low noise amplifier (LNA) using two stage cascading topology to obtain high gain. Inductive degeneration and peaking inductor techniques are used to obtain wideband matching an...
CHIRP REDUCTION IN A SINGLE MODE DM-SQW-DFB LASER OPERATED AT SECOND QUANTIZATION STATE
We have observed the reduction in the chirp parameters (gain compression and above threshold a-factor) by operating the single quantum well laser at second quantization state. In this study, the carrier density at thresh...
LOW POWER RF SINGLE BALANCED MIXER WITH HIGH CONVERSION GAIN FOR ISM BAND APPLICATIONS
This paper involves the design and simulation of a single balanced down conversion mixer from a Gilbert cell mixer using a source degeneration inductor and folded structure in 65nm CMOS Technology. The proposed single ba...
MEMRISTOR EMULATOR USING MCP3208 AND DIGITAL POTENTIOMETER
In this paper, we are using memristor emulator made up of a Digital Potentiometer (DigPot) and microcontroller (Arduino). Mostly the emulator is composed of off-the-shelf electronic component. Here we are using MCP3208 m...