Power Efficient Weighted Modulo 2n+1 Adder
Journal Title: International Journal of Computer & organization Trends(IJCOT) - Year 2013, Vol 3, Issue 11
Abstract
The comparison of three different architectures for modulo 2n+1 adders are introduced in this paper. The first two architecture can be implemented different power consumptions, while maintain the same delay. The partitioned Sklansky structure compared to previous architecture can be implemented less power consumptions, while maintain the different delay and gate counts. The modulo adder 2n+1 adders can be easily derived by adding extra logic of modulo 2n-1 adder. Power efficient modulo 2n+1 adders are appreciated in a variety of computer applications such as cryptography,RNS. The modulo 2n+1 adder is synthesized using Xilinx 9.1i tool and implemented FPGA spartan2 kit. Keywords- Sklansky-style parallel prefix adder, kogge-stone parallel prefix adder, FPGA Spartan 2 kit ,VLSI.
Authors and Affiliations
C. Venkataiah , C. Vijaya Bharathi , M. Narasimhulu
Keywords
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