Power Gating Techniques for Nano-Scale Devices
Journal Title: GRD Journal for Engineering - Year 2017, Vol 2, Issue 9
Abstract
Power consumption is one of the major issues in CMOS technology. ITRS reports that leakage power may dominate the total power consumption. As technology feature size shrinks, the static power dominates the dynamic power consumption. This is known as the sub-threshold leakage which rises by creating a weak inversion channel between drain and source. Gate oxide thickness reduces as technology decreases which increases the sub-threshold leakage. Along with sub-threshold leakage there is an increase in ground bounce noise. This paper reviews different stacking techniques proposed in other papers. But each of those papers had certain trade-offs. So, a combination of the existing techniques has been implemented to have minimal sub-threshold leakage, ground bounce noise and propagation delay
Authors and Affiliations
Srujan Tirupati, Praveen Nimmagadda
Keywords
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- EP ID EP227621
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