Pulse Triggered Flip-Flop Design With Conditional Pulse Enhancement
Journal Title: International Journal of Research in Computer and Communication Technology - Year 2013, Vol 2, Issue 8
Abstract
In this paper a new technique is proposed based on the comparison between Conventional Transistorized Flip-flop and Data transition Look ahead D flip flop here we are checking the working of CDMFF and the conventional D Flip-flop after that we are analyzing the characteristic comparison using power & area constraints after that we are proposing a Negative Edgetriggered flip-flop named as Proposed Negative Edge Triggered Flip-Flop Design (STDFF) with reduced number of transistors which will reduce the overall power area as well as delay. The simulations are done using Microwind & DSCH analysis software tools and the result between all those types are listed below. Our proposed system simulations are done under 50nm technology and the results are tabulated below. In that our proposed system is showing better output than the other flip-flops compared here.
Authors and Affiliations
A V S Swathi, M Lakshmi Prasanna Rani
Keywords
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- EP ID EP27611
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