Reduced Power In Processor Cache Using New Cache Architecture
Journal Title: International Journal of Research in Computer and Communication Technology - Year 2013, Vol 2, Issue 12
Abstract
In recent years, many high-performance microprocessors employ cache write-through policy for performance improvement. Multi-core chips also allow higher performance at lower energy. A multi-core processor implements multiprocessing in a single physical package. At the same manner it tolerance good soft errors. New cache architecture referred to as way-tagged cache to improve the energy efficiency of write-through caches. Cache write-through policy is inherently tolerant to soft errors because the data at all related levels of the cache hierarchy are always kept consistent. Many highperformance microprocessor designs have adopted the write-through policy by maintaining the way tags of L2 cache in the L1 cache during read operations, the proposed technique enables L2 cache to work in an equivalent direct-mapping manner during write hits, which account for the majority of L2 cache accesses. A processor cache is a cache used by the central processing unit of a computer to reduce the average time to access memory. Way-tagged cache achieves better energy efficiency with no performance degradation can reduce this energy consumption. In a set-associative cache, each set in the cache contains multiple line frames. The number of line Frames in each set is referred to as the number of ways in the cache. The collection of corresponding Line frames across all sets in the cache is a way in the cache. Tag Addresses are stored in special tag memories that are not directly visible to the CPU. The cache tag memories on each access to determine if the access is a hit or a miss. The idea of way tagging can be applied to existing low-power cache design Techniques to further improve energy efficiency.
Authors and Affiliations
V. Muthu Revathy, A. Nandini, V. P. M. B. Aarthi, S. Ellammal
Keywords
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