Reduction of Common Mode Voltage in Three Level Diode Clamped Inverter
Journal Title: International Journal for Research in Applied Science and Engineering Technology (IJRASET) - Year 2017, Vol 5, Issue 3
Abstract
In this paper, an approach to reduce common mode voltage (CMV) at output terminal of the inverter using simple sinusoidal PWM technique is proposed. Multilevel inverter (MLI) is more suitable in high & medium power application, CMV is produced at the time of operation in output terminal of inverter. This paper realizes the implementation of PD-SPWM technique to reduce CMV for three level diode clamped inverter (DCMLI). A good transaction between the quality of the output voltage & the magnitude of CMV is achieved in this paper. The main purpose of the paper is to study and implement hardware circuit of three level DCMLI using MOSFET’s. However, the output voltage is smoother with a three level converter. Simulation & experimental result presented to confirm the effectiveness of the proposed technique to control CMV.
Authors and Affiliations
Shiwani Rasekar, Heena Sheikh
Keywords
Related Articles
- EP ID EP23576
- DOI http://doi.org/10.22214/ijraset.2017.3116
- Views 281
- Downloads 8
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