STRUCTURAL BUILDINGS IN K- VALUED LOGIC OPTOELECTRONIC DISPLAY INFORMATION DEVICES
Journal Title: Телекомунікаційні та інформаційні технології - Year 2018, Vol 103, Issue 3
Abstract
The ways of hardware implementation of digital logic elements based on k-valued logic, used in systems of information display of telecommunication equipment for increasing the speed of data processing are offered. The possibility of using a multiplexer circuit as a logical basis in the general case for k-valued logic and for a triple logic in a separate case is shown. On the example of the ternary logic, the possible use of a direct and inverse multiplexer as a complete logical basis is mathematically justified. Using this basis, any complex kvalued logical function can be represented as a multi-tier hierarchical structure in which the element is an elementary multiplexer. The use of multiplexers simplifies the design and synthesis of complex digital circuits with a large number of input variables. The variants of the structural scheme of the ternary full sequential adder using a multiplexer with a single control signal are proposed. To reduce hardware costs and reduce power consumption, an adder circuit has been developed based on a multiplexer with two control signals. To implement a digital element with memory, a block diagram of the ternary D - trigger has been developed using the k- value multiplexer as a basic element. An example of building a digital automaton in a 3-value logic is given, which from a sequence of input signals detects a given combination and provides an output control signal. The proposed method for constructing circuits of digital combinational devices and logical devices with memory based on k -digit multiplexers will allow increasing the capacity and speed of processing large data arrays.
Authors and Affiliations
Dmytro Hololobov
Keywords
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