Test power optimization with redundant transition test patterns in Digital Circuit

Abstract

In the design modelling of a DFT interface, the controlling and access operation defines the performance of BIST interfacing. In a DFT application, data stored in the BIST units are mapped to given query input and an output is developed as a match signal to which as decision is made. in the process of DFT operation, to obtain a faster matching and low power consumption, a new search approach and pattern alignment logic is defined. To improve the storage capacity of a DFT unit, a multi page interface is proposed. To the defined unit a new fault tolerance approach is integrated for a reliable, low power and fast processing DFTapplication.

Authors and Affiliations

Y. Sreenivasula Goud, Dr. B. K. Madhavi

Keywords

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  • EP ID EP439094
  • DOI 10.9790/2834-1303010108.
  • Views 147
  • Downloads 0

How To Cite

Y. Sreenivasula Goud, Dr. B. K. Madhavi (2018). Test power optimization with redundant transition test patterns in Digital Circuit. IOSR Journal of Electronics and Communication Engineering(IOSR-JECE), 13(3), 1-8. https://europub.co.uk./articles/-A-439094