Low Power Design Techniques in CMOS Circuits : A Review Journal title: International Journal for Research in Applied Science and Engineering Technology (IJRASET) Authors: Agrakshi Mehta, Suman Rani Subject(s): Engineering, Applied Linguistics
High Speed Noise Tolerant Domino Circuit For Wide Fan-in AND-OR Gates Journal title: International Journal for Research in Applied Science and Engineering Technology (IJRASET) Authors: K.Rajasri, M.Manikandan Subject(s): Engineering, Applied Linguistics
Design of Multioutput High Speed Adder Using Domino Circuit Journal title: International Journal for Research in Applied Science and Engineering Technology (IJRASET) Authors: K. Rajasri, S. Kalpana Subject(s): Engineering, Applied Linguistics
Ground Bouncing Noise Reduction in Combinational Circuits Journal title: International Journal for Research in Applied Science and Engineering Technology (IJRASET) Authors: G Sudhakar, B Venkanna, N Bhojanna Subject(s): Engineering, Applied Linguistics
Analysis of Different Types of Domino Logic: A Review Journal title: International Journal for Research in Applied Science and Engineering Technology (IJRASET) Authors: Eesh Mittal, Nagendra Sah Subject(s): Engineering, Applied Linguistics
Power Dissipation Reduction In CMOS Circuits Using Power Gating Scheme Journal title: International Journal of Research in Computer and Communication Technology Authors: D. Abhilash Sharon ,M. Santhosh Gideon Subject(s): Computer and Information Science, Telecommunications
Design And Implementation of CMOS Adder Cell With Reduced Leakage Power Technique In 90nm Technology Journal title: International Journal of Research in Computer and Communication Technology Authors: J Manohar, Ch. Janardhan, K.V. Ramanaiah Subject(s): Computer and Information Science, Telecommunications
LEAKAGE POWER OPTIMIZED SEQUENTIAL CIRCUITS FOR USE IN NANOSCALE VLSI SYSTEMS Journal title: Indian Journal of Computer Science and Engineering Authors: M. Janaki Rani , Dr. S. Malarkkan Subject(s):
A Novel Technique for Glitch and Leakage Power Reduction in CMOS VLSI Circuits Journal title: International Journal of Advanced Computer Science & Applications Authors: Pushpa Saini, Rajesh Mehra Subject(s):
Synthesis of a MSP430 Microcontroller Core using Multi-Voltage Techniques Journal title: INTERNATIONAL JOURNAL OF ENGINEERING TRENDS AND TECHNOLOGY Authors: M.Aravind kumar#1 , Ch.V.V.S.Srinivas#2 , C.V.Pradeep Kumar Reddy#3,Abdul Rahaman shaik#4 , K.Rames... Subject(s):
Low Power Design of Standard Digital Gate Design Using Novel Sleep Transistor Technique Journal title: International Journal of Modern Engineering Research (IJMER) Authors: Kusum Tomar1 , A.S.M.Tripathi2 Subject(s):
PATTERN AND POSITION DEPENDENT GATE LEAKAGE AND REDUCTION TECHNIQUE Journal title: ICTACT Journal on Microelectronics Authors: Sreekala K S, Krishna Kumar S Subject(s):
Particle Swarm Optimization Algorithm for Leakage Power Reduction in VLSI Circuits Journal title: International Journal of Electronics and Telecommunications Authors: V.Leela Rani, M.Madhavi Latha Subject(s):
Overcoming the Leakage Power Analysis Attack Using Higher Order DPA-Resistant AES-Masking Journal title: Scholars Journal of Engineering and Technology Authors: Malini S, Manju Priya K, Shiney Immaculate S Subject(s):
Implementation of Low Power 8T SRAM Cell with Dynamic Feedback Control using AVLG Technique Journal title: International Journal of engineering Research and Applications Authors: Devarapalli Mounika, Akondi Narayana Kiran Subject(s):
