Monte-Carlo simulation of a 10T Full adder for propagation delay optimizations Journal title: International Journal of Research in Computer and Communication Technology Authors: S.Sasi Kiran, B. Ravichander, J. Ramaiah, G. Vinatha Subject(s): Computer and Information Science, Telecommunications
PERFORMANCE EVALUATION OF AN EFFICIENT SINGLE EDGE TRIGGERED D FLIP FLOP BASED SHIFT REGISTERS USING CNTFET Journal title: Indian Journal of Computer Science and Engineering Authors: Ravi.T , Kannan.V Subject(s):
LOW POWER NOVEL HYBRID ADDERS FOR DATAPATH CIRCUITS IN DSP PROCESSOR Journal title: Indian Journal of Computer Science and Engineering Authors: B. Sathiyabama , Dr. S. Malarkkan Subject(s):
Energy-Efficient, Noise-Tolerant CMOS Domino VLSI Circuits in VDSM Technology Journal title: International Journal of Advanced Computer Science & Applications Authors: Salendra.Govindarajulu, Dr.T.Jayachandra Prasad, C.Sreelakshmi, Chandrakala, U.Thirumalesh Subject(s):
Design of Low Power High Speed D-Latch Using Stacked Inverter and Sleep Transistor at 32nm CMOS Technology Journal title: International Journal of Trend in Scientific Research and Development Authors: Subject(s): Biological Sciences, Computer and Information Science, Engineering, Mathematics, Agricultural Engineering, Management, Engineering, Multidisciplinary
Comparative Analysis of Efficient Designs of D Latch using 32nm CMOS Technology Journal title: International Journal of Trend in Scientific Research and Development Authors: Subject(s): Biological Sciences, Computer and Information Science, Engineering, Mathematics, Agricultural Engineering, Management, Engineering, Multidisciplinary
A Novel Design of Low-Power 1-Bit CMOS Full-Adder Cell using XNOR and MUX Journal title: INTERNATIONAL JOURNAL OF MANAGEMENT & INFORMATION TECHNOLOGY Authors: Dayadi Lakshmaiah, Dr. M.V. Subramanyam, Dr. K.Sathya Prasad Subject(s):
