Low Power Design Techniques in CMOS Circuits : A Review Journal title: International Journal for Research in Applied Science and Engineering Technology (IJRASET) Authors: Agrakshi Mehta, Suman Rani Subject(s): Engineering, Applied Linguistics
Design of Low Power FPGA using Autonomous Power Gating and LEDR Encoding Journal title: International Journal of Research in Computer and Communication Technology Authors: Sandhya Rani.P, Venkata Satish.N Subject(s): Computer and Information Science, Telecommunications
Comparative Study on Power Gating Techniques for Lower Power Delay Product, Smaller Power Loss, Faster Wakeup Time Journal title: EAI Endorsed Transactions on Industrial Networks and Intelligent Systems Authors: Minh Huan Vo Subject(s): Computer and Information Science, Data Communication and Networks, Industrial Management
Leakage Power Reduction Through Hybrid Multi-Threshold CMOS Stack Technique In Power Gating Switch Journal title: International Journal of Advanced Research in Computer Engineering & Technology(IJARCET) Authors: R.Divya , J.Muralidharan Subject(s):
Low Power Design of Standard Digital Gate Design Using Novel Sleep Transistor Technique Journal title: International Journal of Modern Engineering Research (IJMER) Authors: Kusum Tomar1 , A.S.M.Tripathi2 Subject(s):
Design Optimization of Memristor Based 6T and 7T SRAM Cells using Sleep transistor at Nanoscale Techniques Journal title: International Journal of Computational Engineering and Management IJCEM Authors: Vishwas Mishra and Shalini Singh Subject(s):
A Review and Comparative Study of Different Low Power Consumption Techniques Journal title: International Journal of Science and Research (IJSR) Authors: Subject(s):
