A Note on Linear based Set Associative Cache address System
Journal Title: International Journal on Computer Science and Engineering - Year 2012, Vol 4, Issue 8
Abstract
Based on the system request or application request a set of word is loaded on the cache memory. When the system is switched off the cache history gets abscond. The performance of CPU is based on the factors such as cache hit, write through cache, write back, cache memory mapping technique, CPU speed, bandwidth, cache memory size etc., Some of the standard cache addresses mapping techniques are set associative, associative and direct mapping technique. This paper proposes a novel idea of set associative cache address mapping using linear equation. The standard set associative mapping is remapped with linear set associative for to secure the data in a non sequential portion by having the standard mapping execution time. This is mainly focus on to design the cache enhancement and improvement.
Authors and Affiliations
Chandramowliswaran N , Srinivasan. S , Chandra Segar. T
Keywords
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