An Improved Low Power Counter Design with Clock Enable
Journal Title: International Journal of engineering Research and Applications - Year 2017, Vol 7, Issue 6
Abstract
This paper presents an improved low power design of a 4-bit Johnson Counter which is designed using and Clock enable method. The proposed design shows a power reduction of 5mW as compared to the conventional Johnson counter which is 7mW. Pulse triggered flip flop employed in the proposed design can save power up to 28.57% as compared to the conventional design. All the simulations were carried out using Xilinx software in SIM module.
Authors and Affiliations
Varsha Dewre, Rakesh Mandliya
Keywords
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