Implementation of a High-Speed RSD Based ECC Processor with Vedic Multipliers
Journal Title: International Journal for Research in Applied Science and Engineering Technology (IJRASET) - Year 2016, Vol 4, Issue 5
Abstract
In this paper, an exportable application-specific instruction-set elliptic curve cryptography processor based on redundant signed digit representation is proposed. The processor employs extensive pipelining techniques for Karatsuba–Ofman method to achieve high throughput multiplication. Furthermore, an efficient modular adder without comparison and a high throughput addition/subtraction, which results in a short data path for maximized frequency, are implemented. We have proposed a novel recursive decomposition algorithm for addition to obtain high-throughput digit-serial implementation. The synthesis results for field programmable gate array (FPGA) and application specific integrated circuit (ASIC) realization of the proposed designs and competing existing designs are compared.
Authors and Affiliations
Chitra A, Sangeethalakshmi K, Prabhakar K
Keywords
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- EP ID EP22156
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