Partial Reconfiguration Using FPGA – A Review
Journal Title: GRD Journal for Engineering - Year 2016, Vol 1, Issue 0
Abstract
This paper proposes a review on Partial reconfiguration using Field Programmable Gate Array (FPGA). By downloading configuration bit files Partial Dynamic Reconfiguration (PDR) dynamically modifies the hardware portion of the device. Both FPGA and reconfigurable are used to speed up the performance of various applications. This makes the FPGA to be used in new dimension with an advantage of more flexibility. Literature surveys on various reconfigurable computing techniques were performed with the results and discussions. A more suitable method can be selected based on the applications. A main contribution of this review paper is that it summarizes the current research, key enabling techniques, applications, Research issues and challenges in Partial reconfiguration. All these application are described with its basic block and its implementation.
Authors and Affiliations
M. Jothi, Dr. N. B. Balamurugan, Dr. R. Harikumar
Keywords
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